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High Speed Serial Communication

 

Automated Testing and Debugging

High-speed digital standards are quickly evolving to support the performance demands
of our data driven world. Next generation serial standards and data communication
requirements are bringing new test challenges, pushing the limits of today’s compliance
and debug tools. From design and simulation, analysis, debug, and compliance
testing, Tektronix provides automated electrical test solutions to optimize performance,
speed up validation cycles and accelerate time-to-market.

 

 

 

 

 

PCIe MotherboardAccurate, Repeatable Testing of
High-Performance Computing Standards

The demand for greater data throughput and increased memory capacity continues to grow in such data-intensive markets as data center, artificial intelligence (AI), and high-performance computing. Higher data transfer rates lead to complex designs that push the boundaries of signal integrity and require higher-performance measurements for compliance, debugging and validation. Tektronix's automated test solutions equip engineers to test their latest designs by addressing these challenges with accuracy and repeatability.

PCI Express (PCIe) and CXL

Memory (DDR and LPDDR)

Storage (SAS and SATA)

 

Consumer Electronics

Reduced Time to Test Consumer
Technologies

The pace of innovation is stimulating the demand for newer and faster consumer devices.
The standards underlying their development introduce new test challenges in terms of
increased data rates and design complexity. Tektronix test solutions provide accurate,
repeatable measurements and reduced test times for conformance to the latest
specifications.

Display (DisplayPort and HDMI)

MIPI (M-Phy, D-Phy, C-Phy and UFS)

USB

Thunderbolt

 

 

EthernetComprehensive Tools for Ethernet Device Designs

Ethernet provides network connectivity ranging from hyper-scale data centers and enterprise
systems to automotive and industrial applications. Tektronix offers comprehensive toolsets for
testing, developing, and debugging the physical layer of IEEE 802.3 Ethernet devices in these ecosystems.

Ethernet (10M to 400G and beyond)

 

 

 

JitterAdvanced Measurement and Analysis Tools

Tektronix’ SDLA, PAMJET, and DPOJET software offers powerful signal analysis tools for
high-speed serial standards. Whether analyzing the latest PAM4 signals using PAMJET, de-
embedding waveforms with SDLA, or performing jitter/noise analysis with DPOJET, Tektronix
offers the tools you need.

Jitter Measurement and Timing Analysis (DPOJet)

De-embedding and Receiver Equalization (SDLA)

Electrical and Timing analysis of PAM signals (PAMJet)

 

 

 

 

 

Resources

PCIe USB LPDDR

PCIe Gen6 PAM4 Signaling

Meeting USB4 Compliance and Characterization
Test Challenges

Solving Key LPDDR5 DRAM Test Challenges

Prepare for the next PCI Express inflection point by viewing this discussion of validation requirements for PCI Express Gen6. We review newly introduced transmitter measurements including SNDR and uncorrelated jitter and show a stressed eye calibration for receiver testing at 32GBaud PAM4 using real lab data.

View our USB4 Compliance and Characterization Test webinar to learn how you can address the measurement challenges associated with the new USB4 standard.
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Solve Key LPDDR5 DRAM Test Challenges, for test tips and techniques to meet the design challenge  posed by this mobile memory standard.
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Mobile Device Communication Ethernet DDR

Automated Compliance Testing of MIPI D-PHY
Physical Layer

112 Gb/s Ethernet Demonstration with
Synopsys Transmitter PHY

DDR5 Memory Validation and Debug

Get an overview of the MIPI D-PHY physical layer and electrical signaling, including key tests and discussion of probing, fixtures, and test setups.
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With the approaching ratification of 802.3ck, electrical characterization needs are particularly increasing. This demo highlights next generation testing for end-to-end characterization of a 53 GBd Synopsys® 112G PHY IP transmitter.

The industry is transitioning from DDR4 to the next generation of the DDR memory standard. DDR5 introduces new challenges that must be overcome
in its implementation and verification.
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